Logic devices are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of large systems often requires the use of EDA tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) flow are synthesis, mapping, placement, and routing.
Prior to synthesis, a description of the system may also be generated by the EDA tool. The description of the system may include a register transfer level (RTL) description to describe the operation of synchronous digital circuits. In RTL design, a circuit's behavior is defined in terms of the flow of signals between hardware registers and the logical operations performed on those signals. RTL abstraction is used in hardware description languages such as Verilog and very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) to create high-level representations of a circuit, from which lower-level representations and can be derived.
In the past, EDA tools with schematic-based graphical user interface provided limited options to control data paths in a design for a system. This made it challenging for a designer to implement control structures such as irregular loops. As a result, the designer would often need to directly input control structure using RTL. This would require additional time and effort from the designer and prevent the designer from utilizing some of the features of the EDA tool.